H.264解码器中帧内预测模块的硬件设计Intra Prediction Module Design in H. 264 Decoder
代路伟,罗家融
摘要(Abstract):
为了消除图像编码过程中出现的空间冗余,H.264编码器采用了帧内预测技术提高压缩率。而在解码过程中,帧内预测解码部分占用了较多的时钟资源和硬件资源。本文针对协议中帧内预测编码的算法,通过分析,对算法进行化简,并根据邻块的空间相关性特点,设计了一种并行结构。经过功能验证与FPGA验证,表明该解码模块在消耗硬件资源增加17%的基础上,可以比常规解码模块提高45%的解码速度,较好的满足性能要求。
关键词(KeyWords): H.264解码器;帧内预测;硬件实现
基金项目(Foundation):
作者(Author): 代路伟,罗家融
参考文献(References):
- [1]Atul Puri,Chen Xuemin.Video Coding Using the H.264/MPEG-4 AVC Compressing Standard[J].Signal Processing:ImageCommucication,2011,(19):793-849
- [2]Sojeong Lim,Hyungwook Kim,Youngkyoung Choi,Sungwook Yu.Fast intra-mode decision method based on DCT coefficients for H.264/AVC[J].Signal,Image and Video Processing,2015,9(2):481-489
- [3]周娅.H.264解码系统设计与关键算法研究[D].武汉:华中科技大学博士学位论文,2011.
- [4]Loukil H,Werda I,Masmoudi N,et al.FPGA Design of an Intra 16×16 Module for H.264/AVC Video Encoder[J].Circuits and Systems,2010,1(01):18-29
- [5]Wang Q,Li Q,Chen S,et al.An optimized hardware architecture for intra prediction in H.264 decoder[C]//ASIC(ASICON),2013 IEEE 10th International Conference on.IEEE,2013:1-4
- [6]胡林峰,于映.H.264/AVC解码端帧内预测的设计与实现[J].微计算机信息,2009,25(9):214-286
- [7]Chuang T.A 59.5 m W Scalable Multi-view Video Decoder Chip for Quad/3D Full HDTV and Video Streaming Applications[C].Solid-State Circuits Conference Digest of Technical Papers(ISSCC),2010:330-331
- [8]Werda I,Dammak T,Grandpierre T,et al.Real-time H.264/AVC baseline decoder implementation on TMS320C6416[J].Journal of Real-Time Image Processing,2012,7(4):215-232
- [9]车文斌.H.264解码器的FPGA验证[D].哈尔滨:哈尔滨工业大学,2013.